A quad flat package (QFP)is one type of a semiconductor package, and FIG. 1 shows the construction of the conventional quad flat package. The quad flat package includes a semiconductor chip 3, a paddle 2 on which the semiconductor chip 3 is mounted, a lead frame 1 having a plurality of leads 1a, 1b provided at both sides of the paddle 2, and a plurality of metal wires 4 for electrically connecting the leads 1a of the lead frame 1 to the semiconductor chip 3. An epoxy molding compound 5 substantially encapsulates the lead frame 1 and has a predetermined thickness. The above-mentioned leads 1a, 1b are classified into an inner lead 1a and an outer lead 1b protruding from the epoxy molding compound.
The fabrication process of the conventional semiconductor package includes a first step for forming a lead frame 1 including leads and a paddle 2, a second step for mounting a semiconductor chip 3 on the paddle 2 of the lead frame 1, a third step for electrically connecting the leads of the lead frame 1 and the semiconductor chip 3 using a plurality of metal wires 4, and a fourth step for encapsulating the lead frame 1 using an epoxy molding compound. Thereafter, a trimming step, and a forming step are subsequently performed. The semiconductor package is then mounted on a printed circuit board, and information can be stored in the semiconductor chip and can be read from the same when voltage is supplied thereto.
However, the conventional semiconductor package is disadvantaged since the paddle 2 has an inclined portion resulting from pressure of an epoxy molding compound during the molding process. The leads can be easily bent by external impact force applied thereto since the leads extend to the outside after the molding process. Hence, the reliability of the semiconductor package is decreased.
In addition, it is difficult to accurately align and mount the semiconductor package having a plurality of extended leads on the printed circuit board. Moreover, the temperature of the semiconductor package increases during the operation of the semiconductor chip when a voltage is supplied to the chip, and the generated heat due to the increased temperature cannot be effectively emitted to the outside, thereby causing malfunctions and errors of the chip.